1. Technical Field
This disclosure relates to memory address decoders, and more particularly to decoder circuits with reduced current leakage.
2. Description of the Related Art
Modern VLSI (Very Large Scale Integration) chips are power constrained. Leakage power is often one factor that contributes to power utilization in a VLSI chip. Memory array decode word line drivers of a VLSI chips often contribute a large amount of power leakage due to the very large number and width of the inverters that make up the word line driver of a memory array decode word line driver. Prior art techniques for reducing leakage power in decode word line drivers typically revolve around implementing the word line drivers with long channel devices or selecting high voltage threshold devices. Both implementations however, slow the overall decode process.